These registers are accessed using the mtpr and mfpr instructions.

RXCS

0x20 Receive Control Register (Read / Write)

D = Done bit (Read Only)
IE = Interrupt enable (Read/Write)

The done bit in the RXCS register is read-only and is set by the keyboard handler whenever a key press is received. It is initialized to 0 at bootstrap time and is cleared whenever

mfpr #RXDB, dst is executed. If the RXCS interrupt enable bit is set by software, an interrupt is generated when done becomes set. Similarly, if done is already set and the software sets interrupt enable , an interrupt is generated.

RXDB

0x21 Receive Data Register (Read Only)

E = Error bit (Read Only)

The data received from the keyboard is stored in the low eight bits. The error bit in the RXDB register is set when the received data contained an error such as overrun or loss of connection. This register is read only.

TXCS

0x22 Transmit Control Register (Read / Write)

R = Ready bit Read Only
IE = Interrupt enable bit Read Write

At Bootstrap time (when MacVax is reset) the ready bit is set to 1. On a

mtpr src, #TXDB instruction, the ready bit is cleared. When the output of the character completes the ready bit is set back to 1. If the interrupt enable bit is set by software, an interrupt is generated when the ready bit is set. If the ready bit is already set and software sets interrupt enable, an interrupt is also generated.

TXDB

0x23 Transmit Data Register (Write Only)

Writing into the TXDB register will cause the character represented by the low byte to be drawn in the I/O window. Writing to the TXDB register when the ready bit is clear may cause the character currently being output to be lost. Note that the MacVAX simulator sends characters asynchronously to the screen. This means that your characters may not appear instantly in the input/output window upon execution of a

mtpr src, #TXDB Several instructions will be executed before the output is completed.