These registers are accessed using the mtpr and mfpr instructions.

SCBB

0x11 System Control Block Base (Read / Write)

SCBB holds the Physical address of the System Control Block The address must be long aligned (the low 2 bits must be 00) . The System Control Block is a page of vectors for aborts, faults, traps, and interrupts.

IPLR

0x12 Interrupt Priority Level Register (Read / Write)

The IPLR accesses bits 20 to 16 of the PS.

ASTR

0x13 Async Trap level (Read/Write)

The ASTR holds the value of the most privileged access mode for which an AST is pending. Only bits 0 to 2 are used. The top bits are ignored on a write and returned as 0 on a read. ASTŐs are serviced on a rei instruction. The register is initialised at boot time to 0x4 (ie No AST pending).

SIRR

0x14 Software Interrupt Request Register (Write Only)

The SIRR is write only. A

mtpr src , #SIRR instruction requests an software interrupt at IPL src. Pending interrupts are summarized in the SISR.

SISR

0x15 Software Interrupt Summary Register (Read / Write)

The SISR holds a summary of the pending software interrupts. The register is cleared at boot time and may be cleared by software using a

mtpr #0, #SISR This is normally considered a read only register. Software interrupts should be requested using the SIRR register not by setting bits in the SISR register directly.