| Purpose: | To maintain a loop count and loop |
| Format: | opcode limit.rx, add.rx, index.mx, displ.bw |
| Operation: |
- index <- index + add;
- if{{ add >= 0 } AND { index <= limit }}
- OR{{ add < 0 } AND { index >= limit }} then
- PC <- PC + sign-extended displ;
|
Condition
Codes: |
N <- index LSS 0;
Z <- index EQL 0;
V <- {Integer Overflow or Floating Overflow};
C <- C; |
| Exceptions: | Integer Overflow;
Floating Overflow
Floating Underflow;
Reserved Operand (Floating Point) |
| Opcodes: |
| 9D | ACBB | Add Compare and Branch Byte |
| 3D | ACBW | Add Compare and Branch Word |
| F1 | ACBL | Add Compare and Branch Long |
| 4F | ACBF | Add Compare and Branch Float |
| 6F | ACBD | Add Compare and Branch Double |
|
| Description: |
The addend operand is added to the index operand and the index operand is replaced by the result. The index operand is compared with the limit operand.
If the addend operand is positive (or 0) and the comparison is less than or equal , or if the addend is negative and the comparison is greater than or equal, the signed-extended branch operand is added to the PC and the PC is replaced by the result. |
| Notes: |
- 1.
- ACB efficiently implements the general FOR or DO loops in high level languages since the sense of the comparison between the index and limit is dependant on the sign of the addend.
- 2.
- On integer overflow, the index operand is replaced by the low order bits of the true result. Comparison and branch determination proceed normally on the updated index operand.
- 3.
- On floating underflow, the index operand is replaced by 0. Comparison and branch determination proceed normally.
- 4.
- On floating overflow, the index operand is replaced by an operand of all 0 bits except for a sign bit of 1 (-0 or reserved operand). N <- 1; z <- 0; V <- 1. The branch is not taken.
- 5.
- On a reserved operand fault, the index operand is unaffected and the condition codes are unpredictable.
- 6.
- Except for 5 above, the C-bit is unaffected.
- 7.
- On a trap, the branch condition will be tested and the PC potentially updated before the exception is taken. Thus, the PC might point to the start of the loop and no the next consecutive instruction.
|