Branch on Condition Instruction

Purpose:To test condition codes and branch
Format:opcode displ.bb
Operation:if condition then PC <- PC + sign extended displ
Condition
Codes:		 N <- N;
Z <- Z;
V <- V;
C <- C;
Exceptions:None
Opcodes:
12Z = 0BNEQBranch on Not Equal Signed
BNEQUBranch on Not Equal Unsigned
13Z = 1BEQLBranch on Equal Signed
BEQLUBranch on Equal Unsigned
14{N OR Z} = 0BGTRBranch on Greater Than Signed
1A{C OR Z} = 0BGTRUBranch on Greater Than Unsigned
18N = 0BGEQBranch on Greater Than or Equal Signed
1EC = 0BGEQUBranch on Greater Than or Equal Unsigned
BCCBranch on Carry Clear
15{N OR Z} = 1BLEQBranch on Less Than or Equal Signed
1B{C OR Z} = 1BLEQUBranch on Less Than or Equals Unsigned
19N = 1BLSSBranch on Less Than Signed
1FC = 1BLSSUBranch on Less Than Unsigned
BCSBranch on Carry Set
1CV = 0BVCBranch on Carry Set
1DV = 1BVSBranch on Carry Set
Description: The condition codes are tested and if the condition indicated by the instruction is true, the sign-extended branch displacement is added to the PC and the PC is replaced by the result
Notes: The displacement is a signed byte. In order to achieve a greater branch displacement, a reverse test, branching over the following instruction, followed by a BRW or a JMP may be used. The assembler pseudo instructions Jxxx, where the J replaces the first B of any of the above instructions, may used to have the assembler perform this substitution when necessary.