BB Instructions

Purpose:To branch on bit test
Format:opcode pos.rl, base.ab, displ.bb
Operation:
teststate = if {BBS} then 1 else 0;
if FIELD(pos, 1, base) EQL teststate then
PC <- PC + sign-extended displ
Condition
Codes:
N <- N;
Z <- Z;
V <- V;
C <- C;
Exceptions:Reserved Operand
Opcodes:
E0BBSBranch on bit Set
E1BBCBrance on bit Clear
Description: The single bit specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the PC and the PC is replaced by the result.
Notes:
1.
A reserved operand fault occurs if pos is greater (unsigned) than 31 and the bit is contained in a register.
2.
On a reserved operand fault, the condition codes are unpredictable.