| Purpose: | To branch on bit test and modify |
| Format: | opcode pos.rl, base.ab, displ.bb |
| Operation: |
- teststate = if {BBSS or BBSC} then 1 else 0;
- newstate = if {BBSS or BBCS} then 1 else 0;
- tmp <- FIELD(pos, 1, base)
- FIELD(pos, 1, base) <- newstate
- if tmp EQL teststate then
- PC <- PC + sign-extended displ
|
Condition
Codes: |
N <- N;
Z <- Z;
V <- V;
C <- C; |
| Exceptions: | Reserved Operand |
| Opcodes: |
| E2 | BBSS | Branch on bit Set and Set |
| E4 | BBSC | Brance on bit Set and Clear |
| E3 | BBCS | Branch on bit Clear and Set |
| E5 | BBCC | Brance on bit Clear and Clear |
|
| Description: |
The single bit specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the PC and the PC is replaced by the result. Regardless of the result, the tested bit is put in the new state indicated by the instruction. |
| Notes: |
- 1.
- A reserved operand fault occurs if pos is greater (unsigned) than 31 and the bit is contained in a register.
- 2.
- On a reserved operand fault, the condition codes are unpredictable.
- 3.
- The modification of the bit is not an interlocked operation. See BBSSI and BBCCI for interlocking instructions.
|