| Purpose: | Branch on test of low bit |
| Format: | opcode src.rl, displ.bb |
| Operation: |
- teststate = if ( BLBS ) then 1 else 0;
- if src bit 0 EQL teststate then
- PC <- PC + sign-extended displ
|
Condition
Codes: |
N <- N;
Z <- Z;
V <- V;
C <- C; |
| Exceptions: | None |
| Opcodes: |
| E8 | BLBS | Branch on low bit Set |
| E9 | BLBC | Branch on low bit Clear |
|
| Description: |
The low bit of the source operand is tested and if equal to the state indicated by the instruction, the sign-extended branch displacement is added to the PC and the PC is replaced with the result. |
| Notes: |
- 1.
- The source operand is taken with long word context although only one bit is tested.
- 2.
- The displacement is a signed byte. In order to achieve a greater branch displacement, a reverse test, branching over the following instruction, followed by a BRW or a JMP may be used. The assembler pseudo instructions Jxxx, where the J replaces the first B of any of the above instructions, may used to have the assembler perform this substitution when necessary.
|