CMPV Instructions

Purpose:

To compare a bit field with a long word.

Format:

opcode startpos.rl, size.rb, base.vb, src.rl

Operation:

CMPV: temp <- sign-extended {extracted field};
CMPZV: temp <- zero-extended {extracted field};
{compare temp with src};

Condition
Codes:

N <- temp LSS src;
Z <- temp EQL src;
V <- 0;
C <- temp LSSU src;

Exceptions:

Reserved Operand

Opcodes:

EC	CMPV	Compare Field
ED	CMPZV	Compare Zero-extended Field

Description:

A field specified by the start position, size and base operands is extracted into a temporary long word and sign-extended for CMPV or zero-extended for CMPZV. The temporary long word is compared with the source operand and the condition codes set or cleared as detailed above.

Notes:


1.: A reserved operand fault occurs if the unsigned size operand is greater than 32 or the bit field is contained in a register and the position operand is outside the range 0 - 31.
2.: On a reserved operand fault the condition codes are unpredictable.
3.: If the base address is a register, the bit field may extend into the next register.
4.: The startpos operand may be negative.