INSQUE Instruction

Purpose:Add entry to the head or tail of an absolute queue
Format:opcode entry.ab, pred.ab
Operation:
if {all memory accesses can be completed} then
{Interrupts off}
succ <- (pred)
(entry) <- succ;
(entry + 4) <- pred;
(succ + 4) <- entry;
(pred) <- entry;
{Interrupts On}
Condition
Codes:
N <- succ LSS pred;
Z <- succ EQL pred; First Entry in the Queue
V <- 0;
C <- succ LSSU pred;
Exceptions:Reserved Operand
Opcodes:
0EINSQUEInsert Entry into Queue
Description: The entry specified by the entry operand is inserted into the queue following the entry specified by the predecessor operand. If the entry inserted was the first one in the queue, the condition code Z-bit is set, otherwise it is cleared. The insertion is a non-interruptible interlocked operation. Before performing any part of the operation, the processor validates that the entire operation can be completed. This ensures that if a memory management exception occurs the queue is left in a consistent state.
Notes:
1.
Because the insertion is non-interruptible, processes running in kernel mode can share queues with interrupt service routines.
2.
The INSQUE and REMQUE instructions are implemented such that cooperating software processes may access a shared list without additional synchronization.
3.
During access validation, any access which cannot be completed results in a memory management exception even though the queue instruction is not started.
4.
A reserved operand fault occurs if any of entry, pred or succ is an address that is not longword aligned, (i.e. for which bits <1:0> NEQU 0). In this case the queue is not altered.
5.
4 above may be false, as might the statement in the description claiming that this operation is interlocked. Later VAX manuals don't mention the interlock and state that absolute queues entries may be on arbitrary boundaries (and therefore cannot be interlocked). MacVAX enforces 4 above, (i.e. queue entries must be long word aligned). The change may be due to the lack of a secondary interlock bit found in the newer relative queue instructions. This extra lock bit is needed to ensure queue integrity in a multi-processor environment.