| Purpose: | To provide access to the Internal Processor Registers |
| Format: |
MTPR opcode src.rl, iprnum.rl
MFPR opcode iprnum.rl, dst.wl
|
| Operation: |
- if PSL<CMD> NEQU kernel then
- Reserved instruction Fault
- MTPR
- IPR[iprnum] <- src;
- MFPR
- dst <- IPR[iprnum];
|
Condition
Codes: |
N <- dst LSS 0;
Z <- dst EQL 0;
V <- 0;
C <- C; |
| Exceptions: | Reserved Instruction
Reserved Operand |
| Opcodes: |
| DA | MTPR | Move To Processor Register |
| DB | MFPR | Move From Processor Register |
|
| Description: |
The specified Internal Processor Register is written to or read from depending on the opcode. Execution may have register specific side effects. |
| Notes: |
- 1.
- A reserved operand fault occurs if the internal processor register does not exist or is Read Only for MTPR or Write Only for MFPR. It also occurs for MTPR, on some invalid operands to some internal processor registers.
- 2.
- A reserved instruction fault occurs if the instruction is executed from any mode other than kernel mode.
- 3.
- See VAX Internal Process Register Summary.
|