REMQUE Instruction

Purpose:Remove an entry from the head or tail of an absolute queue
Format:opcode entry.ab, addr.wl
Operation:
if {all memory accesses can be completed} then
{Interrupts off}
succ <- (entry)
pred <- (entry + 4)
(succ + 4) <- pred;
(pred) <- succ;
{Interrupts On}
Condition
Codes:
N <- succ LSS pred;
Z <- succ EQL pred; Removed the Last Entry
V <- entry EQL pred; Entry was the Head
C <- succ LSSU pred;
Exceptions:Reserved Operand
Opcodes:
0FREMQUERemove Entry from Queue
Description: The queue entry specified by the entry operand is removed from the queue. The address operand is replaced by the address of the entry removed. If there was no entry in the queue to be removed, the condition code V-bit is set; otherwise it is cleared. If the entry was the last element in the queue, the condition code Z-bit is set; otherwise it is cleared. The removal is a non-interruptible interlocked operation. Before performing any part of the operation, the processor validates that the entire operation can be completed. This ensures that if a memory management exception occurs the queue is left in a consistent state.
Notes:
1.
Because the removal is non-interruptible, processes running in kernel mode can share queues with interrupt service routines.
2.
The INSQUE and REMQUE instructions are implemented such that cooperating software processes may access a shared list without additional synchronization.
3.
During access validation, any access which cannot be completed results in a memory management exception even though the queue instruction is not started.
4.
A reserved operand fault occurs if any of entry, pred or succ is an address that is not longword aligned, (i.e. for which bits <1:0> NEQU 0). In this case the queue is not altered.
5.
4 above may be false, as might the statement in the description claiming that this operation is interlocked. Later VAX manuals don't mention the interlock and state that absolute queues entries may be on arbitrary boundaries (and therefore cannot be interlocked). MacVAX enforces 4 above, (i.e. queue entries must be long word aligned). The change may be due to the lack of a secondary interlock bit found in the newer relative queue instructions. This extra lock bit is needed to ensure queue integrity in a multi-processor environment.