SVPCTX Instruction

Purpose:To save a processes context.
Format:opcode
Operation:
If PSL<CMD> NEQU kernel then
Reserved Instruction Fault
{Save process general registers in PCB}
{Save process IPR page table registers in PCB}
{Pop PC and PSL from stack and save in PCB}
{Save process IPR stack registers in PCB}
{Switch to Interrupt stack}
Condition
Codes:
N <- N;
Z <- Z;
V <- V;
C <- C;
Exceptions:Reserved Instruction/td>
Opcodes:
07Save Process Context
Description: The process control block (PCB) is specified by the internal processor register Process Control Block Base (PCBB). The general registers are saved into the PCB. The page table registers describing the process address space are also saved. The PC and PSL, currently on the top of the stack are popped and stored in the PCB. If the SVCPTX instruction is executed when not on the interrupt stack then execution is switched to the interrupt stack and the IPL is maximized to 1.
Notes:
1.
A reserved instruction fault occurs if the instruction is executed from any mode other than kernel mode.
2.
Some processors keep a copy of the process stack pointers in internal registers. In those processors, SVPCTX saves the internal registers from the PCB. Processors that do not keep a copy of all four stack pointers in internal registers keep only the current access mode register in an internal register. The contents of the internal register are switched with the PCB contents whenever the current access mode field changes. MacVAX does have internal copies of all stack registers.
3.
The map, ASTLVL and PME contents of the PCB are not saved because they are rarely changed. Thus not writing them saves overhead.
5.
Between the SVPCTX instruction that saves the state for one process and the LDPCTX instruction that loads the state of another, the internal stack pointers may not be referenced by MFPR or MTPR instructions. This implies that interrupt service routines invoked at a priority higher than the lowest one used for context switching must not reference the process stack pointers.